Network processors are used in a wide variety of products, such as switches, broadband access platforms, web switches, protocol converters, Quality of Service (QoS) provisioning, filtering, firewalls, Virtual Private Networks (VPNs), load balancing, remote monitoring, and intrusion detection, etc. Network processors generally receive a relatively high volume of input data in the form of network packets and perform different operations on the packets depending on the particular network product the processor (or processors) is in.
Some network processors, such as the INTEL IXP (Internet Exchange Processor) family of network processors are programmable. These processors include a number of microengines structured to perform certain tasks. For example, microengines can be small, multi-threaded RISC (Reduced Instruction Set Computer) processors that are capable of being programmed to perform a particular function. The network processors also include one or more Core processors such as the Xscale core which can be used to control the microengines.
Microblocks, as used in this disclosure, are elementary functional units that provide packet processing functionality and operate on a microengine. By themselves, microblocks have limited functionality because they are so specialized. By associating multiple microlocks together, however, more sophisticated functions and powerful network processes can be produced. Typically, a single microengine runs multiple microblocks simultaneously to implement the desired function. The microblocks also have corresponding Core components which reside on the core processor.
Microengines can be programmed to implement microblocks in any conventional manner, such as by loading instructions into the RISC processor from a memory. Typical microengines are programmed by loading instructions from a non-volatile (Flash or EEPROM) memory, although instructions for programming the microengine could be loaded through any acceptable process.
FIG. 1 is a functional block diagram of a network processor 100 including microblocks. Within the processor 100, a microengine 140 includes three microblocks, 124, 128, and 130. The microblock 124 is programmed to perform input Network Address Translation (NAT). The microblock 128 performs IP forwarding, while the microblock 130 performs output NAT. Although their singular functionality is limited, when the microblocks 124, 128, 130 operate together, the microengine 140 is capable of performing complex and useful functions. 104, 108, 110 are Core components corresponding to the Input NAT, IP forward, Output NAT microblocks.
Implementing the microengine 140 to connect multiple microblocks into a group or chaining microblocks to form a function can be performed by suitably configuring a component operating on a core controller and appropriately programming the microengine 140. With reference to FIG. 1, an NAT controller 106 is configured to implement the function of the microengine 140 by configuring the Core components 104, 106, i.e., the NAT controller 106 controls how the microblocks 124, 128, and 130 interact with one another. Additionally, the programmed microengine 140 operates in conjunction with the NAT controller 106, as illustrated in FIG. 1. Presently, to add new functions to the network processor 100, additional core components must be added, each statically configured at compile time to control a topology of a collection of programmed microblocks running on a microengine.
Embodiments of the invention address these and other limitations of the prior art.